The present invention relates to a digital communication system for transmitting transmission data of a frame structure, such as a mobile communication system which employs a code division multiple access (CDMA), transmitting and receiving devices for the system, and a frame synchronization detection circuit.
In digital communications, a frame structure which creates one block for every certain time period is frequently used for the purpose of error detection, the use of correction symbol, multiplication of time of control signal and the like.
In this case, it is necessary to take a frame synchronization between transmission and reception of signals. For the frame synchronization, conventionally, a known synchronization pattern is inserted in advance at a head of each frame as shown in FIG. 10 on a transmission side, and the synchronization pattern is detected on a reception side.
The detection of the synchronization pattern on the reception side, can be realized by taking a correlation between a reception data and a synchronization pattern prepared on the reception side. This process is done by the matched filter.
A matched filter generally has a structure of a transverse filter such as shown in FIG. 11, and has taps of the same number as that the symbol number (represented by h in Example shown in FIG. 10) which constitutes the synchronization pattern. A g-number (g=hxe2x88x921) of delay portions 20 (20-1 to 20-g) are arranged respectively between the taps, and the delay time of these is the same as the chip cycle. Further, multipliers 21 (21-1 to 21-h) are connected respectively to the taps, and coefficients corresponding to the symbols P (P0 to Phxe2x88x921) of the synchronization pattern are respectively multiplied. The outputs from the multipliers 21 are added up by an adder 22, thus obtaining a detection output.
The detection output obtained by such a matched filter has a waveform, for example, as shown in FIG. 12.
Here, a significantly high level of the detection output indicates all of the symbols of a synchronization pattern are appearing in the taps, which is the timing by which the synchronization pattern was detected. Therefore, the incoming timing of the synchronization pattern, that is, a frame timing is detected.
In order to enhance the detection accuracy of the frame timing in such a method, it suffices only if the number of symbols of the synchronization pattern should be increased.
However, if the number of symbols is increased, the number of taps of a matched filter, required to take the correlation is increased, thus increasing the size of the circuit of the matched filter, as well as the consumption current.
Under these circumstances, the following method has been proposed so as to increase the number of symbols of the synchronization pattern without increasing the number of taps.
According to this method, as shown in FIG. 13, a basic pattern PA consisting of symbols (Sa0 to Samxe2x88x921) of a symbol number (m symbols) which is less than a symbol number necessary as a synchronization pattern, is repeated for an integer number of times (n times), and thus a synchronization pattern of a necessary length (mxc3x97n symbols) is formed.
For the synchronization detection based on the synchronization pattern thus formed, a synchronization detection circuit such as shown in FIG. 14 is used.
That is, first, a matched filter 11 corresponding to the basic pattern PA is used, and the basic pattern PA is detected. Therefore, when m=4, for example, the output from the matched filter 11 will take a waveform as shown in FIG. 15. A waveform in which four peaks are created at a cycle period Tr of the basic pattern PA, is created.
Here, while output signals from the matched filter 11 are delayed by a k-number (k=nxe2x88x921) of delay units 12 (12-1 to 12-k) connected in series, each by the cycle period Tr of the basic pattern, the outputs from the matched filter 11 and the outputs from the delay portions 12 are added up by the adder 14.
With this operation, the level of the outputs from the adder 14, that is, the detection outputs, peaks at the timing of all of four peaks having such as a waveform as shown in, for example, FIG. 15, being input to the adder 14, and therefore the synchronization can be detected.
Here, the number of taps necessary for the matched filter 11 is m, which is the same number as that of symbols of the basic pattern PA, whereas the number of taps necessary for a matched filter constituted by the delay portions 12 and the adder 14 is n. Therefore, the detection of a synchronization pattern of mxc3x97n symbols can be achieved with the (m+n) number of taps.
However, with this method, even if a pattern having a small correlation in different positions is used as a basic pattern PA, this basic pattern is repeated so as to generate a large correlation at positions where time axes deviate. Consequently, the detection output will take a waveform having a plurality of peaks P11 to P17 as shown in FIG. 16.
Of these peaks, the timing of the peak P11 which is at the maximum level, becomes a detection timing for the synchronization pattern; however since the level difference as compared to the other peaks is small, the detection efficiency will not very much be improved.
The object of the present invention is to provide a digital communication system capable of performing a synchronization detection at high accuracy with a simple structure, a reception device and a frame synchronization detection circuit.
In order to achieve the above-described object, there is provided, according to the present invention, a digital communication system having a transmission device: comprising synchronization pattern generating means consisting of, for example, a basic pattern memory portion and a synchronization pattern generating portion, for generating a synchronization pattern which is made by arranging a predetermined basic pattern consisting of a combination of a predetermined number of symbols and a reversal basic pattern made by reversing a polarity of each symbol of the basic pattern, in an order according to a predetermined reversal pattern which is a combination of a predetermined number of reversal presence data indicating a non-reversal position and a reversal position, and framing means such as a frame forming section, for sectionalizing transmission data and adding the synchronization pattern generated by the synchronization pattern generating means, thereby structuralizing the transmission data in a frame.
The reception device includes a frame synchronization detection circuit consisting of a first matched filter having taps in a same number as the number of symbols contained in the basic pattern and taps in a same number as the number of focused symbols set at least a part of the symbols contained in the basis pattern, in which a delay time between taps is the same as the time between the focused symbols, and a tap coefficient is set in accordance with the focused symbols, and a second matched filter having tap in a same number of the number of basic patterns and reversal basic patterns contained in the synchronization pattern, in which a delay time between taps is the same as an arrangement cycle of the basic pattern and the reversal basic pattern in the basic pattern, and either one of two predetermined values having different polarities from each other is set as the tap coefficient to correspond to the reversal pattern, which are connected in series.
As a result, the frame position of the transmission data is indicated by a synchronization pattern obtained by arranging a predetermined basic pattern consisting of a combination of a predetermined number of symbols and a reversal basic pattern made by reversing a polarity of each symbol of the basic pattern, in an order according to a predetermined reversal pattern which is a predetermined reversal pattern.
In the reception device, the frame synchronization is performed by detecting the synchronization pattern. A process of taking a correlation of focused symbols of the basic pattern and reversal basic pattern, performed by the first matched filter in accordance with the focused symbols of the basic pattern, and a process of taking a correlation of a reversal basic pattern, performed by the second matched filter in accordance with the reversal pattern are carried out in series one after another, and thus the synchronization pattern is detected.
The reversal pattern is a combination of two types of reversal presence data of different polarities from each other, and therefore when the reversal patterns do not match with those in the second matched filter, reversal presence data cancel out with each other, to reduce the output level of the second matched filter.
According to the present invention, where the number of reversal presence data contained in the reversal pattern is n, a pattern of a combination of By (y=0, 1, . . . , nxe2x88x922, nxe2x88x921), that is, for example {xe2x88x921, 1, 1, 1}, which makes the following formula minimum, is selected,   Max  ⁢      {                  "LeftBracketingBar"                              ∑                          y              =              0                                      n              -              1                                ⁢                      xe2x80x83                    ⁢                      By            ·                          B                              y                +                1                                                    "RightBracketingBar"            ⁢              (                              i            =            1                    ,                      2            ⁢                          xe2x80x83                        ⁢            …                    ⁢                      xe2x80x83                    ,                      n            -            2                          )              }  
when y+ixe2x89xa7n, By+i=0.
As a result, while all of the reversal patterns are not present in the second matched filter, the output level of the second matched filter is suppressed to minimum.
Further, a synchronization pattern transmitted by the transmission device of the present invention is detected by a frame synchronization detection circuit consisting of a matched filter having taps in a same number as the number of focused symbols contained in the synchronization pattern set as a part of the symbols contained in the basis pattern, in which a delay time between taps is the same as the time between the focused symbols, and a tap coefficient is set in accordance with the focused symbols, and a matched filter having tap in a same number of the number of symbols contained in the synchronization pattern, in which a delay time between taps is the same as a cycle of the symbol, and the tap coefficient is set to correspond to the basic pattern.
Therefore, with the conventional frame synchronization detection circuit, the synchronization pattern can be detected.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.